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Public Types | 公共成员函数 | 静态公共成员函数 | 私有成员函数 | Private Attributes | 所有成员列表

Atomic32< T > Class Template Reference 内存

#include <atomictypes.h>

详细描述

template<typename T>
class maxon::Atomic32< T >

Atomic 32 bit integer template.

= Relaxed Ordering : Relaxed ordering means that stores to or loads from a memory location can be reordered by the CPU which means that other threads may observe a completely different order of loads and stores than what your thread seems to do.

= Acquire-Release Ordering : If another thread has released a store on a memory location it is guaranteed that after a load with acquire memory order all following loads will see the (relaxed) stores that preceded the release. Furthermore subsequent loads or stores will not be speculatively executed before this load.

= Sequentially Consistent Ordering : As the name implies operations with this ordering appear in the same order to other threads. This comes at the cost of relatively expensive synchronization between the CPU cores.

By default all memory accesses in C++ are relaxed, any write or read to a variable can be reordered by the CPU. Please note that even if your target CPU does not change the order of memory accesses the C compiler may do so. x86 style CPUs adhere to acquire-release ordering for most memory accesses as long as you don't make use of SSE/AVX. This means that multi threaded code without atomic variables appears to run just fine as long as the compiler doesn't reorder accesses. Of course this code might fail miserably on other platforms (e.g. ARM) or when a new compiler performs optimizations. Therefore you should use AtomicInt*‍/AtomicPtr for variables that are shared by different threads.

Public Types

using  ValueType = T

公共成员函数

MAXON_IMPLICIT   Atomic32 (T value=T())
T  Get () const
void  Set (T newValue)
T  Load () const
void  Store (T newValue)
T  LoadRelaxed () const
void  StoreRelaxed (T newValue)
T  LoadAcquire () const
void  StoreRelease (T newValue)
T  LoadConsume () const
Bool   TryCompareAndSwap (T newValue, T compare)
T  Swap (T newValue)
T  SwapAdd (T add)
T  SwapIncrement ()
T  SwapSubtract (T sub)
T  SwapDecrement ()
T  SwapOr (T orValue)
T  SwapAnd (T andValue)

静态公共成员函数

static Bool   TryCompareAndSwap (T volatile *v, T newValue, T compare)
static T  Swap (T volatile *v, T newValue)
static T  Load (T volatile *v)
static void  Store (T volatile *v, T newValue)
static T  LoadRelaxed (T volatile *v)
static void  StoreRelaxed (T volatile *v, T newValue)
static T  LoadAcquire (T volatile *v)
static void  StoreRelease (T volatile *v, T newValue)
static T  LoadConsume (T volatile *v)
static T  SwapAdd (T volatile *v, T add)
static T  SwapIncrement (T volatile *v)
static T  SwapDecrement (T volatile *v)
static T  SwapOr (T volatile *v, T orValue)
static T  SwapAnd (T volatile *v, T andValue)

私有成员函数

  MAXON_DISALLOW_COPY_AND_ASSIGN ( Atomic32 )

Private Attributes

T volatile  _value

Member Typedef Documentation

◆  ValueType

using ValueType = T

构造函数 & 析构函数文档编制

◆  Atomic32()

MAXON_IMPLICIT Atomic32 ( T  value = T() )

成员函数文档编制

◆  MAXON_DISALLOW_COPY_AND_ASSIGN()

MAXON_DISALLOW_COPY_AND_ASSIGN ( Atomic32 < T >  )
private

◆  Get()

T Get ( ) const

Default routine to get an atomic value. It is identical to Load() with sequentially consistent memory order. Other routines might deliver improved performance.

返回
Read memory location content.

◆  Set()

void Set ( T  newValue )

Default routine to set an atomic value. It is identical to Store() with sequentially consistent memory order. Other routines might deliver improved performance.

参数
[in] newValue Value to be stored.

◆  Load() [1/2]

T Load ( ) const

Atomic load with sequentially consistent memory order.

返回
Read memory location content.

◆  Store() [1/2]

void Store ( T  newValue )

Atomic store with sequentially consistent memory order.

参数
[in] newValue Value to be stored.

◆  LoadRelaxed() [1/2]

T LoadRelaxed ( ) const

Atomic load with relaxed memory order. This load is completely unordered (might be prefetched). You should only use it within the same thread when guarded with preceding acquire load or a fence. Fences are implicitly created by TryCompareAndSwap, Swap, SwapAdd, SwapIncrement, SwapDecrement and by locks.

返回
Read memory location content.

◆  StoreRelaxed() [1/2]

void StoreRelaxed ( T  newValue )

Atomic store with relaxed memory order. This store is completely unordered. You should only use it within the same thread when guarded by a following release store or a fence.

参数
[in] newValue Value to be stored.

◆  LoadAcquire() [1/2]

T LoadAcquire ( ) const

Atomic load with acquire memory order. If another thread has released a store on this location it is guaranteed that after a load with acquire memory order all following loads will see the (relaxed) stores that preceded the release. Furthermore subsequent loads or stores will not be speculatively executed before this load. This is equivalent to a relaxed load followed by a MemoryFenceAcquire() .

返回
Read memory location content.

◆  StoreRelease() [1/2]

void StoreRelease ( T  newValue )

Atomic store with release memory order. As soon as another thread reads on this location using LoadAcquire() and obtains the stored value it is guaranteed that all prior (relaxed) stores are visible to it. This is equivalent to a MemoryFenceRelease() followed by a relaxed store.

参数
[in] newValue Value to be stored.

◆  LoadConsume() [1/2]

T LoadConsume ( ) const

Atomic load with consume memory order. If another thread has released a store on this location it is guaranteed that after a load with consume memory order that reads the value stored direct dependencies are synchronized (e.g. if the value is a pointer to a structure you can safely access the elements of the structure that have been written before the release). This means that unrelated loads following this method might be reordered by the compiler or the CPU and can be executed before it. For most CPU architectures this the same instruction as an ordinary load which implies no performance penalty compared to a load with relaxed memory order.

返回
Read memory location content.

◆  TryCompareAndSwap() [1/2]

Bool TryCompareAndSwap ( T  newValue ,
T  compare  
)

Atomic compare and swap with sequentially consistent memory order. If the previous memory location value equals compare newValue is written to the memory location and true is returned. If the memory location contained a different value it is not changed and false will be returned. If the value is exchanged this call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] newValue Value to be stored if memory location contains compare.
[in] compare Value to compare with memory location.
返回
True if the memory value was exchanged.

◆  Swap() [1/2]

T Swap ( T  newValue )

Atomic swap with sequentially consistent memory order. Exchanges the value of the memory location with newValue and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] newValue Value to be stored.
返回
Previous value of the memory location.

◆  SwapAdd() [1/2]

T SwapAdd ( T  add )

Atomic add with sequentially consistent memory order. Adds the specified value to the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] add Value to be added.
返回
Previous value of the memory location.

◆  SwapIncrement() [1/2]

T SwapIncrement ( )

Atomic increment with sequentially consistent memory order. Increments the value of the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

返回
Previous value of the memory location.

◆  SwapSubtract()

T SwapSubtract ( T  sub )

Atomic subtract with sequentially consistent memory order. Subtracts the specified value from the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] sub Value to be subtracted.
返回
Previous value of the memory location.

◆  SwapDecrement() [1/2]

T SwapDecrement ( )

Atomic decrement with sequentially consistent memory order. Decrements the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

返回
Previous value of the memory location.

◆  SwapOr() [1/2]

T SwapOr ( T  orValue )

Atomic or with sequentially consistent memory order. Ors the specified value to the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] orValue Value to be ored.
返回
Previous value of the memory location.

◆  SwapAnd() [1/2]

T SwapAnd ( T  andValue )

Atomic and with sequentially consistent memory order. Ands the specified value to the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] andValue Value to be anded.
返回
Previous value of the memory location.

◆  TryCompareAndSwap() [2/2]

static Bool TryCompareAndSwap ( T volatile *  v ,
T  newValue ,
T  compare  
)
static

Atomic compare and swap with sequentially consistent memory order. If the previous memory location value equals compare newValue is written to the memory location and true is returned. If the memory location contained a different value it is not changed and false will be returned. If the value is exchanged this call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] v Pointer to the memory location.
[in] newValue Value to be stored if memory location contains compare.
[in] compare Value to compare with memory location.
返回
True if the memory value was exchanged.

◆  Swap() [2/2]

static T Swap ( T volatile *  v ,
T  newValue  
)
static

Atomic swap with sequentially consistent memory order. Exchanges the value of the memory location with newValue and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] v Pointer to the memory location.
[in] newValue Value to be stored.
返回
Previous value of the memory location.

◆  Load() [2/2]

static T Load ( T volatile *  v )
static

Atomic load with sequentially consistent memory order.

参数
[in] v Memory location.
返回
Read memory location content.

◆  Store() [2/2]

static void Store ( T volatile *  v ,
T  newValue  
)
static

Atomic store with sequentially consistent memory order.

参数
[in] v Memory location.
[in] newValue Value to be stored.

◆  LoadRelaxed() [2/2]

static T LoadRelaxed ( T volatile *  v )
static

Atomic load with relaxed memory order. This load is completely unordered (might be prefetched). You should only use it within the same thread when guarded with preceding acquire load or a fence. Fences are implicitly created by TryCompareAndSwap, Swap, SwapAdd, SwapIncrement, SwapDecrement and by locks.

参数
[in] v Memory location.
返回
Read memory location content.

◆  StoreRelaxed() [2/2]

static void StoreRelaxed ( T volatile *  v ,
T  newValue  
)
static

Atomic store with relaxed memory order. This store is completely unordered. You should only use it within the same thread when guarded by a following release store or a fence.

参数
[in] v Memory location.
[in] newValue Value to be stored.

◆  LoadAcquire() [2/2]

static T LoadAcquire ( T volatile *  v )
static

Atomic load with acquire memory order. If another thread has released a store on this location it is guaranteed that after a load with acquire memory order all following loads will see the (relaxed) stores that preceded the release. Furthermore subsequent loads or stores will not be speculatively executed before this load. This is equivalent to a relaxed load followed by a MemoryFenceAcquire() .

参数
[in] v Memory location.
返回
Read memory location content.

◆  StoreRelease() [2/2]

static void StoreRelease ( T volatile *  v ,
T  newValue  
)
static

Atomic store with release memory order. As soon as another thread reads on this location using LoadAcquire() and obtains the stored value it is guaranteed that all prior (relaxed) stores are visible to it. This is equivalent to a MemoryFenceRelease() followed by a relaxed store.

参数
[in] v Memory location.
[in] newValue Value to be stored.

◆  LoadConsume() [2/2]

static T LoadConsume ( T volatile *  v )
static

Atomic load with consume memory order. If another thread has released a store on this location it is guaranteed that after a load with consume memory order that reads the value stored direct dependencies are synchronized (e.g. if the value is a pointer to a structure you can safely access the elements of the structure that have been written before the release). This means that unrelated loads following this method might be reordered by the compiler or the CPU and can be executed before it. For most CPU architectures this the same instruction as an ordinary load which implies no performance penalty compared to a load with relaxed memory order.

参数
[in] v Memory location.
返回
Read memory location content.

◆  SwapAdd() [2/2]

static T SwapAdd ( T volatile *  v ,
T  add  
)
static

Atomic add with sequentially consistent memory order. Adds the specified value to the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] v Memory location.
[in] add Value to be added.
返回
Previous value of the memory location.

◆  SwapIncrement() [2/2]

static T SwapIncrement ( T volatile *  v )
static

Atomic increment with sequentially consistent memory order. Increments the value of the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

返回
Previous value of the memory location.

◆  SwapDecrement() [2/2]

static T SwapDecrement ( T volatile *  v )
static

Atomic decrement with sequentially consistent memory order. Decrements the value of the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] v Memory location.
返回
Previous value of the memory location.

◆  SwapOr() [2/2]

static T SwapOr ( T volatile *  v ,
T  orValue  
)
static

Atomic or with sequentially consistent memory order. Ors the specified value to the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] v Memory location.
[in] orValue Value to be ored.
返回
Previous value of the memory location.

◆  SwapAnd() [2/2]

static T SwapAnd ( T volatile *  v ,
T  andValue  
)
static

Atomic and with sequentially consistent memory order. Ands the specified value to the memory location and returns the previous value. This call enforces a sequentially consistent memory order which means that it might require potentially expensive synchronization between the CPUs.

参数
[in] v Memory location.
[in] andValue Value to be anded.
返回
Previous value of the memory location.

Member Data Documentation

◆  _value

T volatile _value private